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1 ltc1293/ltc1294/ltc1296 single chip 12-bit data acquisition system the ltc1293/4/6 is a family of data acquisition systems which contain a serial i/o successive approximation a/d converter. it uses ltcmos tm switched capacitor technol- ogy to perform either 12-bit unipolar, or 11-bit plus sign bipolar a/d conversions. the input multiplexer can be configured for either single ended or differential inputs (or combinations thereof). an on-chip sample and hold is included for all single ended input channels. when the ltc1293/4/6 is idle it can be powered down in applica- tions where low power consumption is desired. the ltc1296 includes a system shutdown output pin which can be used to power down external circuitry, such as signal conditioning circuitry prior to the input mux. the serial i/o is designed to communicate without external hardware to most mpu serial ports and all mpu parallel i/o ports allowing up to eight channels of data to be transmitted over as few as three wires. d u escriptio s f ea t u re n software programmable features unipolar/bipolar conversion differential/single ended inputs msb-first or msb/lsb data sequence power shutdown n built-in sample and hold n single supply 5v or 5v operation n direct 4-wire interface to most mpu serial ports and all mpu parallel ports n 46.5khz maximum throughput rate n system shutdown output (ltc1296) n resolution ..................................................... 12 bits n fast conversion time ............ 12 m s max over temp. n low supply current ........................................ 6.0ma key specificatio s u u a o pp l ic at i ty p i ca l 12-bit data acquisition system with power shutdown ltcmos tm is a trademark of linear technology corporation ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd + r b 5.1k r2 1.2m r1 10k 1/4 lt1014 r2 1.2m c2 1 m f 350 w strain gauge bridge +5v 47 m f 1n4148 mpu ltc1296 v cc sso clk cs d out d in ref + ref agnd v three additional strain gauge inputs can be accommodated using the other amplifiers in the lt1014 ltc1293 ta01 2n3906 74hc04
2 ltc1293/ltc1294/ltc1296 a u g w a w u w a r b s o lu t exi t i s supply voltage (v cc ) to gnd or v C ................................................... 12v negative supply voltage (v C ) ..................... C6v to gnd voltage analog and reference inputs ............................ (v C ) C0.3v to v cc + 0.3v digital inputs ......................................... C0.3v to 12v digital outputs........................... C0.3v to v cc + 0.3v power dissipation ............................................. 500mw operating temperature range ltc1293/4/6bc, ltc1293/4/6cc, ltc1293/4/6dc ....................................... 0 c to 70 c ltc1293/4/6bi, ltc1293/4/6ci, ltc1293/4/6di .................................... C40 c to 85 c ltc1293/4/6bm, ltc1293/4/6cm, ltc1293/4/6dm ............................... C55 c to 125 c storage temperature range .................. C65 c to 150 c lead temperature (soldering, 10 sec.) ................ 300 c (note 1 and 2) wu u package / o rder i for atio ltc1293bcs LTC1293CCS ltc1293dcs order part number order part number ltc1293bmj ltc1293cmj ltc1293dmj ltc1293bij ltc1293cij ltc1293dij ltc1293bin ltc1293cin ltc1293din ltc1293bcn ltc1293ccn ltc1293dcn ltc1294bcs ltc1294ccs ltc1294dcs ltc1296bcs ltc1296ccs ltc1296dcs ltc1294bin ltc1294cin ltc1294din ltc1294bcn ltc1294ccn ltc1294dcn ltc1294bmj ltc1294cmj ltc1294dmj ltc1294bij ltc1294cij ltc1294dij ltc1296bin ltc1296cin ltc1296din ltc1296bcn ltc1296ccn ltc1296dcn ltc1296bmj ltc1296cmj ltc1296dmj ltc1296bij ltc1296cij ltc1296dij 1 2 3 4 5 6 7 8 9 10 top view s package 20-lead plastic so 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd dv cc av cc clk cs d out d in ref + ref agnd v 1 2 3 4 5 6 7 8 top view s package 16-lead plastic sol 16 15 14 13 12 11 10 9 ch0 ch1 ch2 ch3 ch4 ch5 com dgnd v cc clk cs d out d in v ref agnd v 1 2 3 4 5 6 7 8 top view j package 16-lead ceramic dip n package 16-lead plastic dip 16 15 14 13 12 11 10 9 ch0 ch1 ch2 ch3 ch4 ch5 com dgnd v cc clk cs d out d in v ref agnd v 1 2 3 4 5 6 7 8 9 10 top view j package 20-lead ceramic dip n package 20-lead plastic dip 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc sso clk cs d out d in ref + ref ? agnd v 1 2 3 4 5 6 7 8 9 10 top view s package 20-lead plastic so 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc sso clk cs d out d in ref + ref agnd v 1 2 3 4 5 6 7 8 9 10 top view j package 20-lead ceramic dip n package 20-lead plastic dip 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd dv cc av cc clk cs d out d in ref + ref agnd v
3 ltc1293/ltc1294/ltc1296 parameter conditions min typ max min typ max min typ max units offset error (note 4) l 3.0 3.0 3.0 lsb linearity error (inl) (notes 4, 5) l 0.5 0.5 0.75 lsb gain error (note 4) l 0.5 1.0 4.0 lsb minimum resolution for which no l 12 12 12 bits missing codes are guaranteed analog and ref input range (note 7) (v C )C0.05v to v cc + 0.05v v on channel leakage current (note 8) on channel = 5v l 1 1 1 m a off channel = 0v on channel = 0v l 1 1 1 m a off channel = 5v off channel lekage current (note 8) on channel = 5v l 1 1 1 m a off channel = 0v on channel = 0v l 1 1 1 m a off channel = 5v (note 3) co verter a d ultiplexer characteristics uu w ltc1293/4/6c ltc1293/4/6d ltc1293/4/6b symbol parameter conditions min typ max units f clk clock frequency v cc = 5v (note 6) 0.1 1.0 mhz t smpl analog input sample time see operating sequence 2.5 clk cycles t conv conversion time see operating sequence 12 clk cycles t cyc total cycle time see operating sequence (note 6) 21 clk cycles +500ns t ddo delay time, clk to d out data valid see test circuits l 160 300 ns t dis delay time, cs - to d out hi-z see test circuits l 80 150 ns t en delay time, clk to d out enabled see test circuits l 80 200 ns t hdi hold time, d in after clk - v cc = 5v (note 6) 50 ns t hdo time output data remains valid after clk 130 ns t f d out fall time see test circuits l 65 130 ns t r d out rise time see test circuits l 25 50 ns t whclk clk high time v cc = 5v (note 6) 300 ns t wlclk clk low time v cc = 5v (note 6) 400 ns t sudi set-up time, d in stable before clk - v cc = 5v (note 6) 50 ns t sucs set-up time, cs before clk - v cc = 5v (note 6) 50 ns t whcs cs high time during conversion v cc = 5v (note 6) 500 ns t wlcs cs low time during data transfer v cc = 5v (note 6) 21 clk cycles t ensso delay time, clk to sso see test circuits l 750 1500 ns t dissso delay time, cs to sso - see test circuits l 250 500 ns c in input capacitance analog inputs on channel 100 pf analog inputs off channel 5 digital inputs 5 ltc1293/4/6b ltc1293/4/6c ltc1293/4/6d ac characteristics (note 3)
4 ltc1293/ltc1294/ltc1296 symbol parameter conditions min typ max units v ih high level input voltage v cc = 5.25v l 2.0 v v il low level input voltage v cc = 4.75v l 0.8 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C2.5 m a v oh high level output voltage v cc = 4.75v, i o = C10ma 4.7 v i o = 360 m a l 2.4 4.0 v ol low level output voltage v cc = 4.75v, i o = 1.6ma l 0.4 v i oz high z output leakage v out = v cc , cs high l 3 m a v out = 0v, cs high l C3 i source output source current v out = 0v C20 ma i sink output sink current v out = v cc 20 ma i cc positive supply current cs high l 612 ma i cc positive supply current cs high, ltc1294bc, ltc1294cc, l 510 m a power ltc1294dc, ltc1294bi, shutdown ltc1294ci, ltc1294di, clk off ltc1294bm, ltc1294cm, l 515 m a ltc1294dm i ref reference current cs high l 10 50 m a i C negative supply current cs high l 150 m a i sources sso source current v sso = 0v l 0.8 1.5 ma i sinks sso sink current v sso = v cc l 0.5 1.0 ma e lectr ic al c c hara ter st ics digital a d u i dc (note 3) ltc1293/4/6b ltc1293/4/6c ltc1293/4/6d note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to dgnd, agnd and ref C wired together (unless otherwise noted). note 3: v cc = 5v, v ref + = 5v, v ref C = 0v, v C = 0v for unipolar mode and C5v for bipolar mode, clk = 1.0mhz unless otherwise specified. the l denotes specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 4: these specs apply for both unipolar and bipolar modes. in bipolar mode, one lsb is equal to the bipolar input span (2v ref ) divided by 4096. for example, when v ref = 5v, 1lsb (bipolar) = 2 (5v)/4096 = 2.44mv. note 5: linearity error is specified between the actual end points of the a/d transfer curve. the deviation is measured from the center of the quantization band. note 6: recommended operating conditions. note 7: two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below v C or one diode drop above v cc . be careful during testing at low v cc levels (4.5v), as high level reference or analog inputs (5v) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for inputs near full scale. this spec allows 50mv forward bias of either diode. this means that as long as the reference or analog input does not exceed the supply voltage by more than 50mv, the output code will be correct. to achieve an absolute 0v to 5v input voltage range will therefore require a minimum supply voltage of 4.950v over initial tolerance, temperature variations and loading. note 8 : channel leakage current is measured after the channel selection.
5 ltc1293/ltc1294/ltc1296 supply current vs temperature cc hara terist ics uw a t y p i ca lper f o r c e supply current vs supply voltage supply voltage (v) 4 supply current (ma) 4 6 6 ltc1293 g01 2 0 5 10 8 clk = 1mhz t a = 25? ambient temperature (?) ?0 supply current (ma) 7 8 9 30 70 ltc1293 g02 6 5 ?0 ?0 50 90 110 4 3 10 10 130 clk = 1mhz v cc = 5v reference voltage (v) 1 0.5 0.6 5 ltc1293 g03 0.4 0.3 0.1 2 3 4 0.2 0.9 0.8 offset (lsb = 1/4096 v ref ) 0.7 v os = 0.125mv v cc = 5v v os = 0.250mv unadjusted offset voltage vs reference voltage change in linearity vs reference voltage reference voltage (v) 0 change in linearity (lsb = 1/4096 v ref ) 0.75 1.00 1.25 4 ltc1293 g04 0.50 0.25 0 1 2 3 5 change in gain vs reference voltage reference voltage (v) 0 ?.2 change in gain (lsb = 1/4096 v ref ) ?.0 ?.8 ?.6 ?.4 ?.2 0 1234 ltc1293 g05 5 v cc = 5v ltc1294/6 ltc1293 change in offset vs temperature ambient temperature (?) ?0 magnitude of offset change (lsb) 0.3 0.4 0.5 50 ltc1293 g06 0.2 0.1 0 ?5 0 25 75 125 100 v cc = 5v v ref = 5v clk = 1mhz change in linearity vs temperature change in gain vs temperature minimum clock rate for 0.1lsb error * as the clk frequency is decreased from 1mhz, minimum clk frequency ( d error 0.1lsb) represents the frequency at which a 0.1lsb shift in any code transition from its 1mhz value is first detected. ambient temperature (?) ?0 magnitude of linearity change (lsb) 0.3 0.4 0.5 50 ltc1293 g07 0.2 0.1 0 ?5 0 25 75 125 100 v cc = 5v v ref = 5v clk = 1mhz ambient temperature (?) ?0 magnitude of gain change (lsb) 0.3 0.4 0.5 50 ltc1293 g08 0.2 0.1 0 ?5 0 25 75 125 100 v cc = 5v v ref = 5v clk = 1mhz ambient temperature (?) ?0 minimum clk frequency* (mhz) 0.15 0.20 0.25 50 ltc1293 g09 0.10 0.05 ?5 0 25 75 125 100 v cc = 5v
6 ltc1293/ltc1294/ltc1296 ltc1296 sso source current vs v cc C v sso cc hara terist ics uw a t y p i ca lper f o r c e maximum clock rate vs source resistance d out delay time vs temperature cycle time (?) 10 maximum r filter ** ( w ) 100 1k 10k 10 1k 10k ltc1293 g12 1 100 + +v in c filter 3 1? r filter maximum filter resistor vs cycle time sample and hold acquisition time vs source resistance r source + ( w ) 100 1 s & h aquisition time to 0.02% (?) 10 100 1000 10000 ltc1292 g13 + v in r source + v ref = 5v v cc = 5v t a = 25? 0v to 5v input step input channel leakage current vs temperature ambient temperature (?) ?0 0 input channel leakage current (na) 100 300 400 500 1000 700 ?0 30 50 130 ltc1293 g14 200 800 900 600 ?0 10 70 90 110 on channel off channel guaranteed noise error vs reference voltage reference voltage (v) 0 0 peak-to-peak noise error (lsb) 0.25 0.75 1.00 1.25 2 4 5 2.25 0.50 13 1.50 1.75 2.00 ltc1293 g15 ltc1293/4/6 noise = 200? p-p ltc1296 sso sink current vs v sso 100 0.2 maximum clk frequency* (mhz) 0.4 0.6 0.8 1.0 1k 10k 100k ltc1293 g11 0 v cc = 5v v ref = 5v clk = 1mhz r source ( w ) + +in ?n +v in r source * maximum clk frequency represents the clk frequency at which a 0.1lsb shift in the error at any code transition from its 1mhz value is first detected. ** maximum r filter represents the filter resistor value at which a 0.1lsb change in full scale error from its value at r filter = 0 w is first detected. 0 i sink ( m a) 300 400 500 0.8 ltc1293 g17 200 100 0 0.2 0.4 0.6 1.0 v cc = 5v v sso voltage (v) 0 i source ( m a) 300 400 500 0.4 ltc1293 g16 200 0 0.1 0.2 0.3 0.5 0.7 0.6 v cc = 5v 100 v cc ?v sso voltage (v) ambient temperature (?) ?0 d out delay time from clk (ns) 150 200 250 50 ltc1293 g10 100 0 ?5 0 25 75 125 100 v cc = 5v 50 msb first data lsb first data
7 ltc1293/ltc1294/ltc1296 pi fu ctio s u uu # pin function description 1 C 6 ch0 C ch5 analog inputs the analog inputs must be free of noise with respect to agnd. 7 com common the common pin defines the zero reference point for all single ended inputs. it must be free of noise and is usually tied to the analog ground plane. 8 dgnd digital ground this is the ground for the internal logic. tie to the ground plane. 9v C negative supply tie v C to most negative potential in the circuit (ground in single supply applications). 10 agnd analog ground agnd should be tied directly to the analog ground plane. 11 v ref ref. input the reference inputs must be kept free of noise with respect to agnd. 12 d in data input the a/d configuration word is shifted into this input. 13 d out digital data output the a/d conversion result is shifted out of this output. 14 cs chip select input a logic low on this input enables data transfer. 15 clk clock this clock synchronizes the serial data transfer and controls a/d conversion rate. 16 v cc positive supply this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. ltc1293 # pin function description 1 C8 ch0 C ch7 analog inputs the analog inputs must be free of noise with respect to agnd. 9 com common the common pin defines the zero reference point for all single ended inputs. it must be free of noise and is usually tied to the analog ground plane. 10 dgnd digital ground this is the ground for the internal logic. tie to the ground plane. 11 v C negative supply tie v C to most negative potential in the circuit (ground in single supply applications). 12 agnd analog ground agnd should be tied directly to the analog ground plane. 13, 14 ref C , ref + ref. inputs the reference inputs must be kept free of noise with respect to agnd. the a/d sees a reference voltage equal to the difference between ref + and ref C . 15 d in data input the a/d configuration word is shifted into this input. 16 d out digital data output the a/d conversion result is shifted out of this output. 17 cs chip select input a logic low on this input enables data transfer. 18 clk clock this clock synchronizes the serial data transfer and controls a/d converion rate. 19, 20 av cc, dv cc positive supplies these supplies must be kept free of noise and ripple by bypassing directly to the analog ground plane. av cc and dv cc must be tied together. ltc1294 # pin function description 1 C8 ch0 C ch7 analog inputs the analog inputs must be free of noise with respect to agnd. 9 com common the common pin defines the zero reference point for all single ended inputs. it must be free of noise and is usually tied to the analog ground plane. 10 dgnd digital ground this is the ground for the internal logic. tie to the ground plane. 11 v C negative supply tie v C to most negative potential in the circuit (ground in single supply applications). 12 agnd analog ground agnd should be tied directly to the analog ground plane. 13, 14 ref C , ref + ref. inputs the reference inputs must be kept free of noise with respect to agnd. the a/d sees a reference voltage equal to the difference between ref + and ref C . 15 d in data input the a/d configuration word is shifted into this input. 16 d out digital data output the a/d conversion result is shifted out of this output. 17 cs chip select input a logic low on this input enables data transfer. 18 clk clock this clock synchronizes the serial data transfer and controls a/d conversion rate. 19 sso system shutdown system shutdown output pin will go low when power shutdown is requested. output 20 v cc positive supply this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. ltc1296
8 ltc1293/ltc1294/ltc1296 w i dagra b l o c k (pin numbers refer to ltc1294) load circuit for t ddo , t r and t f load circuit for t ensso and t dissso d out 1.4v 3k w 100pf test point ltc1293 tc02 1.4v 3k w 100pf test point ltc1293 tc08 sso lt1296 test circuits on and off channel leakage current d out 3k 100pf test point 5v t dis waveform 2, t en t dis waveform 1 ltc1293 tc05 load circuit for t dis and t en input shift register sample and hold 12-bit capacitive dac dv cc 20 analog input mux 1 2 3 4 5 6 7 8 9 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com d out 16 clk 18 control and timing 17 cs ltc1293 bd 19 15 ref + 14 dgnd 10 v 11 agnd 12 ref 13 comp 12-bit sar output shift register d in av cc 5v a a i off i on polarity off channels on channel ltc1293 tc1
9 ltc1293/ltc1294/ltc1296 test circuits voltage waveforms for t en cs b11 d out t en 0.8v clk ltc1293 tc07 start 7 8 4 5 6 3 2 1 d in voltage waveform for d out rise and fall times, t r, t f d out 0.4v 2.4v t r t f ltc1293 tc04 voltage waveform for t dis voltage waveform for d out delay time, t ddo clk d out 0.8v t ddo 0.4v 2.4v ltc1293 tc03 voltage waveform for for t ensso clk 0.8v 0.8v ltc1293 tc09 sso t en sso voltage waveform for t dissso d out waveform 1 (see note 1) 2.0v t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. ltc1293 tc06 0.8v 2.4v ltc1293 tc10 sso t dis sso cs
10 ltc1293/ltc1294/ltc1296 start bit the first "logical one" clocked into the d in input after cs goes low is the start bit. the start bit initiates the data transfer and all leading zeroes which precede this logical one will be ignored. after the start bit is received the remaining bits of the input word will be clocked in. further inputs on the d in pin are then ignored until the next cs cycle. u s a o pp l ic at i wu u i for atio the ltc 1293/4/6 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive a/d converter 2. analog multiplexer (mux) 3. sample and hold (s/h) 4. synchronous, half duplex serial interface 5. control and timing logic digital considerations serial interface the ltc1293/4/6 communicates with microprocessors and other external circuitry via a synchronous, half duplex, four-wire serial interface (see operating sequence). the clock (clk) synchronizes the data transfer with each bit being transmitted on the falling clk edge and captured on the rising clk edge in both transmitting and receiving systems. the input data is first received and then the a/d conversion result is transmitted (half duplex). because of input data word the ltc1293/4/6 seven-bit data word is clocked into the d in input on the rising edge of the clock after chip select goes low and the start bit has been recognized. further inputs on the d in pin are then ignored until the next cs cycle. the input word is defined as follows: the half duplex operation d in and d out may be tied together allowing transmission over just 3 wired: cs, clk and data (d in /d out ). data transfer is initiated by a falling chip select (cs) signal. after cs falls the ltc1293/4/6 looks for a start bit. after the start bit is received a 7-bit input word is shifted into the d in input which configures the ltc1293/4/6 and starts the conversion. after one null bit, the result of the conversion is output on the d out line. with the half duplex serial interface the d out data is from the current conversion. after the end of the data exchange cs should be brought high. this resets the ltc1293/4/6 in preparation for the next data exchange. cs d in 1 d in 2 d out 2 d out 1 shift mux address in 1 null bit shift a/d conversion result out ltc1293 ai01 mux address the four bits of the input word following the start bit assign the mux configuration for the requested conver- sion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of the following table. note that in differential mode (sgl/diff = 0) mea- surements are limited to four adjacent input pairs with either polarity. in single ended mode, all input channels are measured with respect to com. only the +inputs have sample and holds. signals applied at the Cinputs must not change more than the required accuracy during the con- version. start sgl/ diff odd/ sign select 1 select 0 uni msbf ps mux address msb first/ lsb first unipolar/ bipolar power shutdown ltc1293 ai02
11 ltc1293/ltc1294/ltc1296 u s a o pp l ic at i wu u i for atio mux address sgl/ diff differential channel selection 00 00 +C 00 01 +C 00 10 +C 00 11 + C 01 00 C+ 01 01 C+ 01 10 C+ 01 11 C + 0 1 2 3 4 5 6 7 table 1a. ltc1294/6 multiplexer channel selection mux address single-ended channel selection 0 1 2 3 4 5 6 7 com 00 00 + C 00 01 + C 00 10 + C 00 11 01 00 C + 01 01 C + 01 10 C + 01 11 table 1b. ltc1293 channel selection 0 1 2 3 4 5 mux address not used not used not used not used unipolar/bipolar (uni) the uni bit determines whether the conversion will be unipolar or bipolar. when uni is a logical one, a unipolar conversion will be performed on the selected input volt- age. when uni is a logical zero, a bipolar conversion will result. the input span and code assignment for each conversion type are shown in the figures below: unipolar output code (uni = 1) odd sign select 1 0 sgl/ diff select 1 0 odd sign 10 00 + C 10 01 + C 10 10 + C 10 11 + C 11 00 + C 11 01 + C 11 10 + C 11 11 + C differential channel selection single-ended channel selection mux address sgl/ diff odd sign select 1 0 sgl/ diff odd sign select 1 0 0 1 2 3 4 5 com 10 00 + C 10 01 + C 10 10 + C 10 11 11 00 + C 11 01 + C 11 10 + C 11 11 0v 1lsb v ref ?lsb v ref ?lsb v ref v in 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ltc1293 ai03b output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 i nput voltage v ref ?1lsb v ref ?2lsb ? ? ? 1lsb 0v i nput voltage (vref = 5v) 4.9988v 4.9976v ? ? ? 0.0012v 0v ltc1293 ai03a unipolar transfer curve (uni = 1)
12 ltc1293/ltc1294/ltc1296 u s a o pp l ic at i wu u i for atio bipolar transfer curve (uni = 0) output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ? 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 input voltage ?lsb ?lsb ? ? ? ?v ref ) + 1lsb ?(v ref ) input voltage (v ref = 5v) ?.0024v ?.0048v ? ? ? ?.9976v ?.00000v output code 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb ? ? ? 1lsb 0v input voltage (v ref = 5v) 4.9976v 4.9851v ? ? ? 0.0024v 0v ltc1293 ai04a bipolar output code (uni = 0) input configuration unipolar mode bipolar mode single-ended lower value com C(ref + C ref C ) + com upper value (ref + C ref C ) + com (ref + C ref C ) + com differential lower value in C C(ref + C ref C ) + in C upper value (ref + C ref C ) + in C (ref + C ref C ) + in C the following discussion will demonstrate how the two reference pins are to be used in conjunction with the analog input multiplexer. in unipolar mode the input span of the a/d is set by the difference in voltage on the ref + pin and the ref C pin. in the bipolar mode the input span is twice the difference in voltage on the ref + pin and the ref C pin. in the unipolar mode the lower value of the input span is set by the voltage on the com pin for single-ended inputs and by the voltage on the minus input pin for differential inputs. for the bipolar mode of operation the voltage on the com pin or the minus input pin set the center of the input span. the upper and lower value of the input span can now be summarized in the following table: the reference voltages ref + and ref C can fall between v cc and v C , but the difference (ref + C ref C ) must be less than or equal to v cc . the input voltages must be less than or equal to v cc and greater than or equal to v C . for the ltc1293 ref C = 0v. the following examples are for a single-ended input con- figuration. example 1: let v cc = 5v, v C = 0v, ref + = 4v, ref C = 1v and com = 0v. unipolar mode of operation. the resulting input span is 0v in + 3v. 1lsb v ref ?lsb v ref ?lsb v ref v in 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ? 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 ?lsb ?lsb ? ref ? ref + 1lsb ? ? ltc1293 ai04b
13 ltc1293/ltc1294/ltc1296 msb-first/lsb-first (msbf) the output data of the ltc1293/4/6 is programmed for msb-first or lsb-first sequence using the msb bit. when the msbf bit is a logical one, data will appear on the d out line in msb-first format. logical zeroes will be filled in indefinitely following the last data bit to accommodate longer word lengths required by some microprocessors. when the msbf bit is a logical zero, lsb first data will follow the normal msb first data on the d out line. in the bipolar mode the sign bit will fill in after the msb bit for msbf = 0 (see operating sequence). power shutdowns (ps) the power shutdown feature of the ltc1293/4/6 is acti- vated by making the ps bit a logical zero. if cs remains low after the ps bit has been received, a 12-bit d out word with example 2: the same conditions as example 1 except com = 1v. the resulting input span is 1v in + 4v. note if in + 3 4v the resulting d out word is all 1s. if in + 1v then the resulting d out word is all 0s. example 3: let v cc = 5v, v C = C5v, ref + = 4v, ref C = 1v and com = 1v. bipolar mode of operation. the resulting input span is C2v in + 4v. for differential input configurations with the same condi- tions as in the above three examples the resulting input spans are as follows: example 1 (diff.): in C in + in C + 3v. example 2 (diff.): in C in + in C + 3v. example 3 (diff.): in C C 3v in + in C + 3v. u s a o pp l ic at i wu u i for atio operating sequence example: differential inputs (ch4 + , ch5 C ), unipolar mode ltc1293 ai05 msb-first data (msbf = 0) msb-first data (msbf = 1) t cyc cs d in d out start sel1 uni ps sgl/ diff odd/ sign msbf t conv t smpl sel0 hi-z filled with zeroes don't care clk don't care b0 b1 b11 clk don't care t cyc cs d in start sel1 uni ps sgl/ diff odd/ sign msbf sel0 don't care d out t conv t smpl hi-z b11 b1 b0 b1 b11 filled with zeroes
14 ltc1293/ltc1294/ltc1296 part number type of interface motorola mc6805s2, s3 spi mc68hc11 spi mc68hc05 spi rca cdp68hc05 spi hitachi hd6305 sci synchronous hd6301 sci synchronous hd63701 sci synchronous hd6303 sci synchronous hd64180 sci synchronous national semiconductor cop400 family microwire ? cop800 family mcrowire/plus ? ns8050u microwire/plus hpc16000 family microwire/plus texas instruments tms7002 serial port tms7042 serial port tms70c02 serial port tms70c42 serial port tms32011* serial port tms32020* serial port tms370c050 spi u s a o pp l ic at i wu u i for atio power shutdown operating sequence example: differential inputs (ch4 + , ch5 C ), unipolar mode and msb-first data all logical ones will be shifted out followed by logical zeroes till cs goes high. then the d out line will go into its high impedance state. the ltc 1293/4/6 will remain in the shutdown mode till the next cs cycle. there is no warm- up or wait period required after coming out of the power shutdown cycle so a conversion can commence after cs goes low (see power shutdown operating sequence). the ltc1296 has a system shutdown output pin (sso) which will go low when power shutdown is activated. the pin will stay low till next cs cycle. microprocessor interfaces the ltc1293/4/6 can interface directly (without external hardware) to most popular microprocessors (mpu) syn- chronous serial formats (see table 1). if an mpu without a dedicated serial port is used, then three of the mpus parallel port lines can be programmed to form the serial link to the ltc1293/4/6. included here are one serial interface example and one example showing a parallel port programmed to form the serial interface. microprocessor interfaces the ltc1293/4/6 can interface directly (without external hardware) to most popular microprocessors (mpu) syn- chronous serial formats (see table 1). if an mpu without a dedicated serial port is used, then three of the mpus parallel port lines can be programmed to form the serial link to the ltc1293/4/6. * requires external hardware ** contact factory for interface information for processors not on this list ? microwire and microwire/plus are trademarks of national semiconductor corp. table 1. microprocessor with hardware serial interfaces compat- ible with the ltc1293/4/6** d in ltc1293 ai06 shutdown* request power shutdown new conversion begins ps msbf uni sel0 odd/ sign sel1/ diff sel1 start don't care ps uni sel0 odd/ sign sel1/ diff sel1 start msbf b0 b11 ? ? ? ? ? ? ? ? ? ? hi-z d out filled with zeroes hi-z clk cs *stopping the clock will help reduce power consumption. cs can be brought high once the din word has been clocked in.
15 ltc1293/ltc1294/ltc1296 interfacing to the parallel port of the intel 8051 family the intel 8051 has been chosen to show the interface between the ltc1293/4/6 and parallel port microproces- sors. usually the signals cs, d in and clk are generated on three port lines and the d out signal is read on a fourth port line. this works very well. one can save a line by tying the d in and d out lines together. the 8051 first sends the start bit and d in to the ltc1294 over the line connected to p1.2. then p1.2 is reconfigured as an input and the 8051 reads back the 12-bit a/d result over the same data line. u s a o pp l ic at i wu u i for atio data exchange between ltc1294 and mc68hc11 motorola spi (mc68hc11) the mc68hc11 has been chosen as an example of an mpu with a dedicated serial port. this mpu transfers data msb- first and in 8-bit increments. the d in word sent to the data register starts the spi process. with three 8-bit transfers, the a/d result is read into the mpu. the second 8-bit transfer clocks b11 through b8 of the a/d conversion result into the processor. the third 8-bit transfer clocks the remaining bits b7 through b0 into the mpu. the data is right justified in the two memory locations. anding the second byte with 0d hex clears the four most significant bits. this operation was not included in the code. it can be inserted in the data gathering loop or outside the loop when the data is processed. hardware and software interface to motorola mc68hc11 cs clk d out mpu received word ltc1293 td01 uni sgl/ diff odd/ even sel 1 sel 0 start msbf ps b3 b7 b6 b5 b4 b2 b0 b1 b11 b10 b9 b8 d in mpu transmit word byte 3 (dummy) byte 2 sgl 0 odd sel 0 sel 1 byte 1 x uni msbf ps x x x x 00 1 start x x x xx x x x byte 3 byte 2 ? ? ? ? ? byte 1 b11 ? ? ? 0 b10 b8 b9 ??? b7 b6 b4 b5 b3 b2 b0 b1 don't care ltc1293 td01a clk d out ltc1294 cs analog inputs do sck miso mc68hc11 d in mosi b2 b1 b0 b3 b4 b6 b7 b5 byte 1 b10 b9 b8 b11 o o oo d out from ltc1294 stored on mc68hc11 ram byte 2 lsb msb #62 #63
16 ltc1293/ltc1294/ltc1296 u s a o pp l ic at i wu u i for atio staa $102a load din into spi, start sck wait2 ldaa $1029 check spi status reg bpl wait2 check if transfer is done ldaa $102a load ltc1294 msbs into acc a staa $62 store msbs in $62 ldaa $52 load dummy din into acc a from $52 staa $102a load dummy din into spi, start sck wait3 ldaa $1029 check spi status reg bpl wait3 check if transfer is done bset $08,x,$01 d0 goes high (cs goes high) ldaa $102a load ltc1294 lsbs in acc staa $63 store lsbs in $63 jmp loop start next conversion label mnemonic operand comments ldaa #$50 configuration data for spcr staa $1028 load data into spcr ($1028) ldaa #$1b config. data for port d ddr staa $1009 load data into port d ddr ldaa #$10 load din word into acc a staa $50 load din data into $50 ldaa #$e0 load din word into acc a staa $51 load din data into $51 ldaa #$00 load dummy din word into acc a staa $52 load dummy din data into $52 ldx #$1000 load index register x with $1000 loop bclr $08,x,$01 d0 goes low (cs goes low) ldaa $50 load din into acc a from $50 staa $102a load din into spi, start sck ldaa $1029 check spi status reg wait1 bpl wait1 check if transfer is done ldaa $51 load din into acc a from $51 mc68hc11 code label mnemonic operand comments hardware and software interface to intel 8051 cs clk data (d in /d out ) ltc1293 td02 1 23 46 57 8 ps bit latched into ltc1294 8051 p1.2 output data to ltc1294 8051 p1.2 reconfigured as input after the 8th rising clk before the 8th falling clk ltc1294 send a/d result back to 8051 p1.2 ltc1294 takes control of data line on 8th falling clk start b11 sgl/ diff odd/ sign sel 1 sel 0 uni msb ps b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 hardware and software interface to intel 8051 ltc1293 td02a d out from ltc1294 stored in 8051 ram 00 0 0 b0 b2 b3 b1 b10 b11 lsb msb r2 r3 b9 b8 b7 b6 b5 b4 clk d out cs analog inputs p1.4 p1.3 8051 d in p1.2 mux address a/d result ltc1294
17 ltc1293/ltc1294/ltc1296 sharing the serial interface the ltc1293/4/6 can share the same 3-wire serial inter- face with other peripheral components or other ltc1293/ 4/6s (figure 3). now, the cs signals decide which ltc1293/ 4/6 is being addressed by the mpu. analog considerations grounding the ltc1293/4/6 should be used with an analog ground plane and single point grounding techniques. do not use wire wrapping techniques to breadboard and evaluate the u s a o pp l ic at i wu u i for atio clr p1.3 clk goes low clr a clear acc rlc a rotate data bit (b3) into acc mov c,p1.2 read data bit into carry rlc a rotate data bit (b2) into acc setb p1.3 clk goes high clr p1.3 clk goes low mov c,p1.2 read data bit into carry rlc a rotate data bit (b1) into acc setb p1.3 clk goes high clr p1.3 clk goes low mov c,p1.2 read data bit into carry setb p1.4 cs goes high rrc a rotate data bit (b0) into acc rrc a rotate right into acc rrc a rotate right into acc rrc a rotate right into acc mov r3,a store lsbs in r3 ajmp cont start next conversion label mnemonic operand comments setb p1.4 cs goes high cont mov a,#87h din word for ltc1294 clr p1.4 cs goes low mov r4,#08h load counter loop1 rlc a rotate din bit into carry clr p1.3 clk goes low mov p1.2,c output din bit to ltc1294 setb p1.3 clk goes high djnz r4,loop1 next din bit mov p1,#04h p1.2 becomes an input clr p1.3 clk goes low mov r4,#09h load counter loop mov c,p1.2 read data bit into carry rlc a rotate data bit (b3) into acc setb p1.3 clk goes high clr p1.3 clk goes low djnz r4,loop next dout bit mov r2,a store msbs in r2 mov c,p1.2 read data bit into carry setb p1.3 clk goes high label mnemonic operand comments 8051 code 8 channels 8 channels 8 channels 3 3 3 3 3-wire serial interface to other peripherals or ltc1293/4/6s 2 10 output port serial data mpu ltc1293 f03 ltc1294 cs ltc1294 cs ltc1294 cs figure 3. several ltc1294 sharing one 3-wire serial interface device. to achieve the optimum performance use a pc board. the analog ground pin (agnd) should be tied directly to the ground plane with minimum lead length (a low profile socket is fine). the digital ground pin (dgnd) also can be tied directly to this ground pin because minimal digital noise is generated within the chip itself. v cc should be bypassed to the ground plane with a 22 m f (minimum value) tantalum with leads as short as possible and as close as possible to the pin. a 0.1 m f ceramic disk also should be placed in parallel with the 22 m f and again with leads as short as possible and as close to v cc as possible. av cc and dv cc should be tied together on the
18 ltc1293/ltc1294/ltc1296 u s a o pp l ic at i wu u i for atio ltc1294. figure 4 shows an example of an ideal ltc1293/ 4/6 ground plane design for a two sided board. of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. bypassing for good performance, v cc must be free of noise and ripple. any changes in the v cc voltage with respect to ground during a conversion cycle can induce errors or noise in the output code. v cc noise and ripple can be kept below 0.5mv by bypassing the v cc pin directly to the analog ground plane with a minimum of 22 m f tantalum capacitor and with leads as short as possible. the lead from the device to the v cc supply also should be kept to a minimum and the v cc supply should have a low output impedance such as obtained from a voltage regulator (e.g., lt323a). for high frequency bypassing a 0.1 m f ceramic disk placed in parallel with the 22 m f is recom- mended. again the leads should be kept to a minimum. figure 5 and 6 show the effects of good and poor v cc bypassing. horizontal: 10 m s/div vertical: 0.5mv/div vertical: 0.5mv/div horizontal: 10 m s/div figure 5. poor v cc bypassing. noise and ripple can cause a/d errors. figure 6. good v cc bypassing keeps noise and ripple on v cc below 1mv cs v cc analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1293/4/6 have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem. if large source resistances are used or if slow settling op amps drive the inputs, take care to insure the transients caused by the current spikes settle completely before the conversion begins. figure 4. ground plane for the ltc1293/4/6 figure 7. analog input equivalent circuit 6th clk - r on = 500 w 8th clk c in = 100pf ltc1293/4/6 ?? input r source + v in + c1 ? input r source v in ? c2 ltc1293 f07 v 22 m f tantalum v cc ltc1293 f04 0.1? ceramic disk analog ground plane 0.1 m f ceramic 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
19 ltc1293/ltc1294/ltc1296 u s a o pp l ic at i wu u i for atio source resistance the analog inputs of the ltc1293/4/6 look like a 100pf capacitor (c in ) in series with a 500 w resistor (r on ). c in gets switched between (+) and (C) inputs once during each conversion cycle. large external source resistors and capacitances will slow the settling of the inputs. it is important that the overall rc time constant is short enough to allow the analog inputs to settle completely within the allowed time. + input settling the input capacitor is switched onto the + input during the sample phase (t smpl , see figure 8). the sample period 2 1/2 clk cycles before a conversion starts. the voltage on the + input must settle completely within the sample period. minimizing r source + and c1 will improve the settling time. if large + input source resistance must be used, the sample time can be increased by using a slower clk frequency. with the minimum possible sample time of 2.5 m s r source + < 1.5k w and c1 < 20pf will provide adequate settling time. C input settling at the end of the sample phase the input capacitor switches to the - input and the conversion starts (see figure 8). during the conversion, the + input voltage is effectively held by the sample and hold and will not affect the conversion result. it is critical that the C input voltage be free of noise and settle completely during the first clk cycle of the conversion. minimizing r source C and c2 will improve settling time. if large C input source resistance must be used the time can be extended by using a slower clk frequency. at the maximum clk frequency of 1mhz, r source C < 250 w and c2 < 20pf will provide adequate settling . input op amps when driving the analog inputs with an op amp it is important that the op amp settles within the allowed time (see figure 8). again the + and C input sampling times can be extended as described above to accommodate slower op amps. most op amps including the lt1006 and lt1013 single supply op amps can be made to settle figure 8. + and C input settling windows d in clk start hi-z ltc1293 f08 cs 1st bit test (? input must settle during this time t smpl (+) input must settle during this time (+) input (? input sgl/ diff msbf ps d out b11 sample hold
20 ltc1293/ltc1294/ltc1296 u s a o pp l ic at i wu u i for atio figure 11. rc input filtering r filter v in ? c filter ltc1293 f11 ltc1293/4/6 "+" "? i idc within the minimum settling windows of 2.5 m s (+ input) and 1 m s(C input) that occurs at the maximum clock rate of 1mhz. figures 9 and 10 show examples of adequate and poor op amp settling. rc input filtering it is possible to filter the inputs with an rc network as shown in figure 11. for large values of c f (e.g., 1 m f) the capacitive input switching currents are averaged into a net dc current. a filter should be chosen with a small resistor and large capacitor to prevent dc drops across the resis- tor. the magnitude of the dc current is approximately i dc = 100pf v in /t cyc and is roughly proportional to v in . when running at the minimum cycle time of 21.5 m s, the input current equals 23 m a at v in = 5v. here a filter resistor of 5 w will cause 0.1lsb of full-scale error. if a larger filter resistor must be used, errors can be reduced by increasing the cycle time as shown in the typical performance char- acteristic curve maximum filter resistor vs cycle time. input leakage current input leakage currents also can create errors if the source resistance gets too large. for example, the maximum input leakage specification of 1 m a (at 125 c) flowing through a source resistance of 1k w will cause a voltage drop of 1mv or 0.8lsb. this error will be much reduced at lower temperatures because leakage drops rapidly (see typical performance characteristic curve input channel leakage current vs temperature). sample and hold single-ended input the ltc1293/4/6 provides a built-in sample and hold (s&h) function for all signals acquired in the single-ended mode (com pin grounded). the sample and hold allows the ltc1293/4/6 to convert rapidly varying signals (see typical performance characteristic curve of s&h acquisi- tion time vs source resistance). the input voltage is sampled during the t smpl time as shown in figure 8. the sampling interval begins as the bit preceding the msbf bit is shifted in and continues until the falling edge of the ps bit is received. on this falling edge the s&h goes into the hold mode and the conversion begins. differential input with a differential input the a/d no longer converts a single voltage but converts the difference between two voltages. the voltage on the selected + input is sampled and held and can be rapidly time varying. the voltage on the C pin must remain constant and be free of noise and ripple throughout the conversion time. otherwise the differencing operation will not be done accurately. the conversion time is 12 clk cycles. therefore a change in the Cin input voltage during this interval can cause con- version errors. for a sinusoidal voltage on the Cin input this error would be: vfv f error max peak clk () () =p () ? ? ? ? 2 12 where f (C) is the frequency of the C input voltage, v peak is its peak amplitude and f clk is the frequency of the clk. horizontal: 20 m s/div horizontal: 500ns/div figure 9. adequate settling of op amp driving analog input figure 10. poor op amp settling can cause a/d errors vertical: 5mv/div vertical: 5mv/div
21 ltc1293/ltc1294/ltc1296 usually v error will not be significant. for a 60hz signal on the C input to generate a 0.25lsb error (300 m v) with the converter running at clk = 1mhz, its peak value would have to be 66mv. rearranging the above equation the maximum sinusoidal signal that can be digitized to a given accuracy is given as: f v v f max error max peak clk ( ) () = p ? ? ? ? ? ? ? ? 2 12 for 0.25lsb error (300 m v) the maximum input sinusoid with a 5v peak amplitude that can be digitized is 0.8hz. unused inputs should be tied to the ground plane. reference input the voltage on the reference input of the ltc1293/4/6 determines the voltage span of the a/d converter. the reference input has transient capacitive switching cur- rents due to the switched capacitor conversion technique (see figure 12). during each bit test of the conversion (every clk cycle) a capacitive current spike will be gener- ated on the reference pin by the a/d. these current spikes settle quickly and do not cause a problem. if slow settling circuitry is used to drive the reference input, take care to insure that transients caused by these current spikes settle completely during each bit test of the conversion. u s a o pp l ic at i wu u i for atio figure 13 and 14 show examples of both adequate and poor settling. using a slower clk will allow more time for the reference to settle. even at the maximum clk rate of 1mhz most references and op amps can be made to settle within the 1 m s bit time. for example the lt1027 will settle adequately or with a 10 m f bypass capacitor at v ref the lt1021 also can be used. vertical: 0.5mv/div vertical: 0.5mv/div figure 14. poor reference settling can cause a/d errors horizontal: 1 m s/div horizontal: 1 m s/div figure 13. adequate reference settling (lt1027) figure 12. reference input equivalent circuit r on 8pf ?40pf ltc1293/4/6 ref+ r out v ref every clk cycle 14 13 ref ltc 1293 f12 reduced reference operation the effective resolution of the ltc1293/4/6 can be in- creased by reducing the input span of the converter. the ltc1293/4/6 exhibits good linearity over a range of refer- ence voltages (see typical performance characteristics curves of change in linearity vs reference voltage and change in gain error vs reference voltage). care must be taken when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the converter. offset and noise are factors that must be considered when operating at low v ref values. for the ltc1293 ref C has been tied to the agnd pin. any voltage drop from the agnd pin to the ground plane will cause a gain error. offset with reduced v ref the offset of the ltc1293/4/6 has a larger effect on the output code when the a/d is operated with a reduced reference voltage. the offset (which is typically a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical performance characteris- tic curve of unadjusted offset error vs reference voltage shows how offset in lsbs is related to reference voltage for a typical value of v os . for example a v os of 0.1mv, which is 0.1lsb with a 5v reference becomes 0.4lsb with
22 ltc1293/ltc1294/ltc1296 u s a o pp l ic at i wu u i for atio a 1.25 reference. if this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the C input to the ltc1293/4/6. noise with reduced v ref the total input referred noise of the ltc1293/4/6 can be reduced to approximately 200 m v peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. this noise is insignificant with a 5v reference input but will become a larger fraction of an lsb as the size of the lsb is reduced. the typical performance characteristic curve of noise error vs reference voltage shows the lsb contribution of this 200 m v of noise. for operation with a 5v reference, the 200 m v noise is only 0.16lsb peak-to-peak. here the ltc1293/4/6 noise will contribute virtually no uncertainty to the output code. for reduced references, the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 1.25v reference, this 200 m v noise is 0.64lsb peak-to-peak. this will reduce the range of input voltages over which a stable output code can be achieved by 0.64lsb. now averaging readings may be necessary. this noise data was taken in a very clean test fixture. any setup induced noise (noise or ripple on v cc , v ref or v in ) will add to the internal noise. the lower the reference voltage used, the more critical it becomes to have a noise- free setup. gain error due to reduced v ref the gain error of the ltc1294/6 is very good over a wide range of reference voltages. the error component that is seen in the typical performance characteristics curve change in gain error vs reference voltage for the ltc1293 is due the voltage drop on the agnd pin from the device to the ground plane. to minimize this error the ltc1293 should be soldered directly onto the pc board. the internal reference point for v ref is tied to agnd. any voltage drop in the agnd pin will make the reference voltage, internal to the device, less than what is applied externally (figure 15). this drop is typically 400 m v due to the product of the pin resistance (r pin ) and the ltc1293 supply current. for example, with v ref = 1.25v this will result in a gain error change of C1.0lsb from the gain error measured with v ref = 5v. figure 15. parasitic pin resistance (r pin ) ltc1293 ref + r pin i cc dac ref v ref agnd ltc1293 f15 reference voltage ltc1293/4/6 ac characteristics two commonly used figures of merit for specifying the dynamic performance of the a/ds in digital signal process- ing applications are the signal-to-noise ratio (snr) and the effective number of bits(enob). snr is the ratio of the rms magnitude of the fundamental to the rms magnitude of all the non-fundamental signals up to the nyquist frequency (half the sampling frequency). the theoretical maximum snr for a sine wave input is given by: snr = (6.02n + 1.76db) where n is the number of bits. thus the snr depends on the resolution of the a/d. for an ideal 12-bit a/d the snr is equal to 74db. a fast fourier transform (fft) plot of the output spectrum of the ltc1294 is shown in figures 16a and 16b. the input (f in ) frequencies are 1khz and 22khz with the sampling frequency (f s ) at 45.4khz. the snr obtained from the plot are 72.7db and 72.5db. rewriting the snr expression it is possible to obtain the equivalent resolution based on the snr measurement. n snr db = ? ? ? ? . . 176 602 this is the so-called effective number of bits (enob). for the example shown in figures 16a and 16b, n = 11.8 bits. figure 17 shows a plot of enob as a function of input frequency. the top curve shows the a/ds enob remains at 11.8 for input frequencies up to f s /2 with 5v supplies.
23 ltc1293/ltc1294/ltc1296 u s a o pp l ic at i wu u i for atio frequency (khz) 0 effective number of bits 9.5 10.0 10.5 60 100 lt1293 f17 9.0 8.5 8.0 20 40 80 11.0 11.5 12.0 f s = 45.4khz ?v supplies +5v supply for +5v supplies the enob decreases more rapidly. this is due predominantly to the 2nd harmonic distortion term. figure 18 shows a fft plot of the output spectrum for two tones applied to the input of the a/d. nonlinearities in the a/d will cause distortion products at the sum and differ- ence frequencies of the fundamentals and products of the fundamentals. this is classically referred to as intermodulation distortion (imd). overvoltage protection applying signals to the ltc1293/4/6s analog inputs that exceed the positive supply or that go below v C will degrade the accuracy of the a/d and possibly damage the device. for example this condition would occur if a signal is applied to the analog inputs before power is applied to the ltc1293/4/6. another example is the input source is operating from different supplies of larger value than the ltc1293/4/6. these conditions should be prevented ei- ther with proper supply sequencing or by use of external circuitry to clamp or current limit the input source. there are two ways to protect the inputs. in figure 19 diode clamps from the inputs to v cc and v C are used. the second method is to put resistors in series with the analog inputs for current limiting. as shown in figure 20a, a 1k w resistor is enough to stand off 15v (15ma for only one channel). if more than one channel exceeds the supplies than the following guidelines can be used. limit the current to 7ma per channel and 28ma for all channels. frequency (khz) 0 magnitude (db) ?0 ?0 0 15 1293 f16a ?0 ?0 20 ?00 ?20 ?40 25 10 5 frequency (khz) 0 magnitude (db) ?0 ?0 0 15 1293 f16b ?0 ?0 20 ?00 ?20 ?40 25 10 5 frequency (khz) 0 magnitude (db) ?0 ?0 0 15 1293 f8 ?0 ?0 20 ?00 ?20 ?40 25 10 5 figure 16b. ltc1294 fft plot f in = 22khz, f s = 45.4khz, snr = 72.5db with 5v supplies figure 16a. ltc1294 fft plot f in = 1khz, f s = 45.4khz, snr = 72.7db with 5v supplies figure 17. ltc1294 enob vs input frequency figure 18. ltc1294 fft plot f in 1 = 5.1khz, f in 2 = 5.6khz, f s = 45.4khz with 5v supplies
24 ltc1293/ltc1294/ltc1296 u s a o pp l ic at i wu u i for atio this means four channels can handle 7ma of input current each. reducing clk frequency from a maximum of 1mhz (see typical performance characteristics curves maxi- mum clk frequency vs source resistance and sample and hold acquisition time vs source resistance) allows the use of larger current limiting resistors. the + input can accept a resistor value of 1k w but the C input cannot accept more than 250 w when the maximum clock fre- quency of 1mhz is used. if the ltc1293/4/6 is clocked at the maximum clock frequency and 250 w is not enough to current limit the C input source then the clamp diodes are recommended (figures 20a and 20b). the reason for the limit on the resistor value is the msb bit test is affected by the value of the resistor placed at the C input (see discussion on analog inputs and the typical performance characteristics curve maximum clk frequency vs source resistance). if v cc and v ref are not tied together, then v cc should be turned on first, then v ref . if this sequence cannot be met connecting a diode from v ref to v cc is recommended (see figure 21). for dual supplies (bipolar mode) placing two schottky diodes from v cc and v C to ground (figure 22) will prevent figure 20a. overvoltage protection for inputs figure 19. overvoltage protection for inputs figure 22. power supply reversal figure 21 power supply reversal from occuring when an input source is applied to the analog mux before power is applied to the device. power supply reversal occurs, for example, if the input is pulled below v C . v cc will then pull a diode drop below ground which could cause the device not to power up properly. likewise, if the input is pulled above v cc , v C will be pulled a diode drop above ground. if no inputs are present on the mux, the schottky diodes are not required if v C is applied first then v cc . because a unique input protection structure is used on the digital input pins, the signal levels on these pins can exceed the device v cc without damaging the device. figure 20b. overvoltage protection for inputs +5v ltc1293 f19 dgnd v agnd v cc 1n4148 diodes ltc1293/4/6 ?v +5v ltc1293 f20a + dgnd v agnd v cc 250 w 1k ltc1293/4/6 ?v +5v ltc1293 f20b + dgnd v agnd v cc ltc1293/4/6 1n4148 diodes 1k ?v +5v ltc1293 f22 dgnd agnd v cc ltc1293/4/6 1n5817 ?v v 1n5817 +5v ltc1293 f21 dgnd agnd v cc ltc1293/4/6 1n4148 +5v ref +
25 ltc1293/ltc1294/ltc1296 unipolar conversion is requested and the data is output msb first. cs is driven at 1/64 the clock rate by the cd4520 and d out outputs the data. the output data from the d out pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of cs (figure 24). vertical: 5v/div horizontal: 2 m s/div clk fills zeroes lsb (b0) null bit msb (b11) figure 24. scope trace of the ltc1294/6 quick look circuit showing a/d output 101010101010 (aaa hex ) ltc1293 ta03 1k 22 m f tantalum ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd dv cc av cc clk cs d out d in ref + ref agnd v ltc1294 + to/from 68hc11 processor +15v a2 lt1006 30.1k** 1 m f 3.92m** 500k zero? trim +15v + a1 lt1101 a=10 +15v 5v out 10 m f 500k 400? trim 12.5k* 12k* 1k* + rplat. * trw-irc mar-6 resistor ?0.1% ** 1% film resistor rplat. = 1k w at 0? ?rosemount #118mf lt1027 digitally linearized platinum rtd signal conditioner to oscilloscope ltc1293 f23 clk en q1 q2 q3 q4 reset v ss v dd reset q4 q3 q2 q1 en clk v in f/64 +5v clock in 1mhz max 22? ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd dv cc av cc clk cs d out d in ref + ref agnd v ltc1294 f cd4520 figure 23. quick look circuit for the ltc1294/6 u s a o pp l ic at i ty p i ca l a quick look circuit for the ltc1294/6 users can get a quick look at the function and timing of the ltc1294/6 by using the following simple circuit (figure 23). v ref is tied to v cc . d in is tied high which means v in should be applied to the ch7 with respect to com. a u s a o pp l ic at i wu u i for atio cs d out
26 ltc1293/ltc1294/ltc1296 u s a o pp l ic at i ty p i ca l micropower, 5000v opto-isolated, multichannel,12-bit data acquisition system is accessed once every two seconds lt1027 5v miso mosi c0 sck c1 10k 10k 9v isolation barrier 4n28s 51k 51k 51k 51k 300 w 5.1k (3) 2n3906 5v 5v 5v 5v 51k 5.1k 10k 10k 10k 10k 150 w 150 w 150 w 150 w 4n28 to additional ltc1294s nc 4n28 *solid tantalum 10 m f* 8 analog inputs 0?v range 2n3904 2n3906 to 68hc11 10k lt1292 ta02 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd dv cc av cc clk cs d out d in ref + ref agnd v ltc1294
27 ltc1293/ltc1294/ltc1296 package descriptio u dimensions in inches (millimeters) unless otherwise noted. 0.290 - 0.320 (7.366 - 8.128) glass sealant 0??15 0.008 ?0.018 (0.203 ?0.457) 0.385 ?0.025 (9.779 ?0.635) 11 3 7 20 16 15 56 10 9 17 14 13 12 1 4 2 19 8 18 0.005 (0.127) 0.025 (0.635) rad typ 0.220 - 0.310 (5.588 - 7.874) 1.060 (26.924) max 0.015 ?0.060 (0.381 ?1.524) 0.160 (4.064) max 0.125 (3.175) min 0.080 (2.032) max 0.014 ?0.026 (0.356 ?0.660) 0.100 ?0.010 (2.540 ?0.254) 0.200 (5.080) max 0.038 ?0.068 (0.965 ?1.727) j20 12/91 j package 16-lead ceramic dip 1 23 4 5 6 7 8 0.220 ?0.310 (5.588 ?7.874) 0.840 (21.336) max 0.005 (0.127) min 16 13 9 10 11 12 14 15 0.025 (0.635) rad typ j16 1291 0.290 ?0.320 (7.366 ?8.128) 0.008 ?0.018 (0.203 ?0.460) 0??15 0.385 ?0.025 (9.779 ?0.635) 0.015 ?0.060 (0.380 ?1.520) glass sealant 0.080 (2.030) max 0.100 ?0.010 (2.540 ?0.254) 0.014 ?0.026 (0.360 ?0.660) 0.038 ?0.068 (0.965 ?1.727) 0.200 (5.080) max 0.160 (4.064) max 0.125 (3.175) min j package 20-lead ceramic dip t jmax q ja 150 c80 c/w t jmax q ja 150 c80 c/w n package 16-lead plastic dip n16 1291 0.260 ?0.010 (6.604 ?0.254) 0.770 (19.558) 16 1 2 3 456 7 8 9 10 11 12 13 14 15 0.009 - 0.015 (0.229 - 0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 ?.015 +0.635 ?.381 8.255 () 0.015 (0.381) min 0.125 (3.175) min 0.130 ?0.005 (3.302 ?0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 ?0.003 (0.457 ?0.076) 0.045 ?0.015 (1.143 ?0.381) 0.100 ?0.010 (2.540 ?0.254) t jmax q ja 110 c 100 c/w information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
28 ltc1293/ltc1294/ltc1296 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 ? linear technology corporation 1992 lt/gp 0392 10k rev 0 package descriptio u dimensions in inches (millimeters) unless otherwise noted. n package 20-lead plastic dip t jmax q ja 110 c 100 c/w t jmax q ja 110 c 150 c/w t jmax q ja 110 c 150 c/w s package 16-lead plastic sol 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.483) typ 0??8?typ see note 0.005 (0.127) rad min 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299 (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) sol16 12/91 note: pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options. see note 0.398 ?0.413 (10.109 ?10.490) 16 15 14 13 12 11 10 9 1 23 4 5 6 78 0.394 ?0.419 (10.008 ?10.643) s package 20-lead plastic sol 0??8?typ see note 0.005 (0.127) rad min 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299 (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) sol20 12/91 note: pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options. see note 0.496 ?0.512 (12.598 ?13.995) 20 19 18 17 16 15 14 13 1 23 4 5 6 78 0.394 ?0.419 (10.008 ?10.643) 910 11 12 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.483) typ n20 0192 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 0.015 +0.635 0.381 8.255 () 0.015 (0.381) min 0.125 (3.175) min 0.130 ?0.005 (3.302 ?0.127) 0.045 ?0.065 (1.143 ?1.651) 0.018 ?0.003 (0.457 ?0.076) 0.065 ?0.015 (1.651 ?0.381) 0.100 ?0.010 (2.540 ?0.254) 0.065 (1.651) typ 17 16 12 15 14 13 11 18 19 20 1 2 3 45 6 7 8910 1.040 (26.416) max 0.260 ?0.010 (6.604 ?0.254)

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